MemPol: Polling-Based Microsecond-Scale Per-Core Memory Bandwidth Regulation

Abstract

In today’s multiprocessor systems-on-a-chip (MPSoC),the shared memory subsystemis a known source of temporal interference.The problem causes logically independent coresto affect each other’s performance,leading to pessimistic worst-case execution time (WCET) analysis. Memory regulation via throttling is one of the most practical techniques to mitigate interference.Traditional regulation schemes rely on a combinationof timer and performance counter interrupts to be delivered andprocessed on the same cores running real-time workload.Unfortunately, to prevent excessive overhead, regulationcan only be enforced at a millisecond-scale granularity. In this work, we presenta novel regulation mechanism from outside the cores that monitors performance countersfor the application core’s activity in main memoryat a microsecond scale. The approach is fully transparentto the applications on the cores,and can be implemented using widely available on-chipdebug facilities. The presented mechanism also allows more complex compositionof metrics to enact load-aware regulation. For instance, it allowsredistributing unused bandwidth between coreswhile keeping the overall memory bandwidthof all cores below a given threshold. We implement our approach on a host of embedded platforms andconduct an in-depth evaluationon the Xilinx Zynq UltraScale+ ZCU102, NXP i.MX8M and NXP S32G2 platformsusing the San Diego Vision Benchmark Suite.

Weifan Chen

Ph.D in Computer Science

My research interests include cyber physical system and artificial intelligence.